Many buyers searching for a double sided wafer lapping machine start with machine size. In practice the wafer material decides most of the process: abrasive, load, speed and acceptance limits. This article explains how silicon and SiC differ, and how to match equipment to the job.
Both silicon and silicon carbide wafers need precision lapping after slicing. Slicing leaves a wavy surface and a damaged layer, and lapping flattens the wafer, makes the two faces parallel and removes slicing damage. One SiC process description removes roughly 50–100 μm from both sides in this step [1]. Because both faces are cut together with a similar removal mechanism, the two surfaces end up similar in profile, roughness and subsurface condition [2].
Silicon is the base material of conventional semiconductor manufacturing. SiC is used in power electronics and other demanding applications, and it is far harder to machine. The same machine can process both, but the strategy cannot be the same. This is why we start from material properties rather than from equipment models.
SiC is much harder than silicon. Approximate Mohs values are about 6.5–7 for silicon and above 9 for SiC, so ordinary abrasives that cut silicon efficiently remove SiC slowly. That raises the bar for abrasive selection and process optimization.
Every lapping process balances material removal rate (MRR) against surface quality. Faster removal reduces cycle time, but it usually deepens damage. For SiC, a slow cut is often accepted because correcting deep damage later in polishing costs more.
Both materials are brittle, and SiC is the less forgiving. Microcracks, edge chipping and a damaged subsurface layer can form during lapping. In 4H-SiC, subsurface damage has been traced to lapping by scratching of diamond particles, and it can act as a nucleation site for threading dislocations during epitaxy [3]. Chamfering the wafer edge before lapping helps avoid chipping and cracking [1].
Initial damage matters downstream. Deeper cracks and scratches mean more polishing stock removal, longer CMP time and a higher chance of residual defects.
Silicon wafers are commonly lapped with loose abrasives such as alumina grit, and double-sided lapping of silicon with loose abrasives has achieved TTV of about 2 μm in published work [2]. Fixed-abrasive approaches have reported TTV near 0.5 μm on silicon [2].
For SiC, diamond is the standard choice because only diamond is clearly harder than the wafer. One process example uses diamond with a mean particle size of 4–12 μm on a double-sided lap machine [1]. Semi-fixed abrasives and resin-bonded plates have also been studied for double-sided SiC lapping [4].
Particle size drives three results at once. Coarser particles raise MRR but increase roughness and damage depth. Finer particles give a smoother finish and shallower damage but slow the cut. Many SiC lines therefore use coarse then fine lapping stages. Validate every abrasive on your own wafer material, incoming condition and target finish, because published values are starting points, not guarantees.
For silicon, lapping pressure, plate speed and processing time all change MRR, and research on double-sided silicon lapping shows these settings directly affect final wafer quality [2]. The key outputs to watch are total thickness variation (TTV), flatness and waviness. Stable load and steady carrier motion matter more than peak removal rate, since small fluctuations appear as thickness variation.
For SiC, excessive mechanical loading raises the risk of cracking and chipping. The goal is to find the load and speed window where removal is acceptable and surface integrity is preserved. Avoid copying silicon settings. Run controlled trials: change one variable at a time, measure thickness, flatness and damage, and record the result.
Pressure and speed control are exactly where machine design matters. Closed-loop pressure feedback and adjustable plate speeds let you hold a tested recipe repeatable from batch to batch.
Four quality targets matter together: thickness uniformity, flatness, roughness and defect control. Lapping mainly sets geometry and removes slicing damage; chemical mechanical polishing (CMP) then removes the remaining damage and produces the final finish. They have different roles and one cannot replace the other. A SiC process example specifies stock polishing after lapping, with a final CMP step before epitaxy [1].
| Target | Set mainly by | Why it matters |
|---|---|---|
| Thickness and TTV | Lapping | Feeds flatness and polishing stock |
| Flatness, waviness | Lapping | Lithography and bonding |
| Roughness | Polishing / CMP | Epitaxy quality |
| Subsurface damage | Lapping sets, CMP removes | Defects in grown layers [3] |
Residual scratches and deep subsurface damage from lapping increase downstream polishing time. In SiC, surface and subsurface condition after lapping affects how well CMP works, so lapping quality should be checked, not only assumed.
Our high-precision double-sided lapping and polishing machine range covers several sizes, including the 6B/6.4B, 9B/9.6B, 12B/13B/13.9B, 16B/18B, 16B/22B, 20B/22B/24B and 28B/30B/32B/35B series. Which series suits a given wafer size, material and batch plan should be confirmed from the equipment specifications and actual process testing, not from the model name. You can also browse the company website, or contact our team with your wafer material, diameter, thickness and target tolerances.
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